Welcome to Devicetree Specification’s documentation!
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1. Introduction
1.1. Purpose and Scope
1.2. Relationship to IEEE™ 1275 and ePAPR
1.3. 32-bit and 64-bit Support
1.4. Definition of Terms
2. The Devicetree
2.1. Overview
2.2. Devicetree Structure and Conventions
2.2.1. Node Names
2.2.2. Generic Names Recommendation
2.2.3. Path Names
2.2.4. Properties
2.3. Standard Properties
2.3.1. compatible
2.3.2. model
2.3.3. phandle
2.3.4. status
2.3.5. #address-cells and #size-cells
2.3.6. reg
2.3.7. virtual-reg
2.3.8. ranges
2.3.9. dma-ranges
2.3.10. name (deprecated)
2.3.11. device_type (deprecated)
2.4. Interrupts and Interrupt Mapping
2.4.1. Properties for Interrupt Generating Devices
2.4.2. Properties for Interrupt Controllers
2.4.3. Interrupt Nexus Properties
2.4.4. Interrupt Mapping Example
3. Device Node Requirements
3.1. Base Device Node Types
3.2. Root node
3.3.
/aliases
node
3.4.
/memory
node
3.5.
/chosen
Node
3.6.
/cpus
Node Properties
3.7.
/cpus/cpu*
Node Properties
3.7.1. General Properties of
/cpus/cpu*
nodes
3.7.2. TLB Properties
3.7.3. Internal (L1) Cache Properties
3.7.4. Example
3.8. Multi-level and Shared Cache Nodes (
/cpus/cpu*/l?-cache
)
3.8.1. Example
4. Device Bindings
4.1. Binding Guidelines
4.1.1. General Principles
4.1.2. Miscellaneous Properties
4.2. Serial devices
4.2.1. Serial Class Binding
4.2.2. National Semiconductor 16450/16550 Compatible UART Requirements
4.3. Network devices
4.3.1. Network Class Binding
4.3.2. Ethernet specific considerations
4.4. Power ISA Open PIC Interrupt Controllers
4.5.
simple-bus
Compatible Value
5. Flat Devicetree Physical Structure
5.1. Versioning
5.2. Header
5.3. Memory Reservation Block
5.3.1. Purpose
5.3.2. Format
5.4. Structure Block
5.4.1. Lexical structure
5.4.2. Tree structure
5.5. Strings Block
5.6. Alignment
6. Devicetree Source Format (version 1)
6.1. Node and property definitions
6.2. File layout
Related Topics
Documentation overview
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